1. Field of the Invention
The present disclosure generally relates to the field of fabrication of integrated circuits, and, more particularly, to manufacturing an interconnect structure requiring a barrier layer formed between a bulk metal and a dielectric, wherein the barrier layer is at least partially formed by self-limiting deposition techniques, such as atomic layer deposition (ALD).
2. Description of the Related Art
In a complex integrated circuit, a very large number of circuit elements, such as transistors, capacitors, resistors and the like, are formed in or on an appropriate substrate, usually in a substantially planar configuration. Due to the large number of circuit elements and the required complex layout of the integrated circuits, generally the electrical connection of the individual circuit elements may not be established within the same level on which the circuit elements are manufactured, but requires one or more additional “wiring” layers, also referred to as metallization layers. These metallization layers generally include metal lines, providing the inner-level electrical connection, and also include a plurality of inter-level connections, also referred to as vias, wherein the metal lines and vias may also be commonly referred to as interconnect structures.
Due to the continuous shrinkage of the feature sizes of circuit elements in modern integrated circuits, the number of circuit elements for a given chip area, that is the packing density, also increases, thereby requiring an even larger increase in the number of electrical interconnections to provide the desired circuit functionality. Therefore, the number of stacked metallization layers increases as the number of circuit elements per chip area becomes larger. Since the fabrication of a plurality of metallization layers entails extremely challenging issues to be solved, such as mechanical, thermal and electrical reliability of many stacked metallization layers that are required, for example, for sophisticated microprocessors, semiconductor manufacturers are increasingly using a metal that allows high current densities and hence allows reducing dimensions of the interconnections. For example, copper is a metal generally considered to be a viable candidate due to its superior characteristics in view of higher resistance against electromigration and significantly lower electrical resistivity when compared with other metals, such as aluminum, that have been used over the last decades. In spite of these advantages, copper also exhibits a number of disadvantages regarding the processing and handling of copper in a semiconductor facility. For instance, copper may not be efficiently applied onto a substrate in larger amounts by well-established deposition methods, such as chemical vapor deposition (CVD), and also may not be effectively patterned by the usually employed anisotropic etch procedures due to its lack of forming volatile etch byproducts. In manufacturing metallization layers including copper, the so-called damascene technique is therefore preferably used wherein a dielectric layer is first applied and then patterned to receive trenches and vias, which are subsequently filled with copper. A further major drawback of copper is its property to readily diffuse in low-k dielectric materials, silicon and silicon dioxide, which is a well-established and approved dielectric material in fabricating integrated circuits.
It is therefore necessary to employ a so-called barrier material in combination with a copper-based metallization to substantially avoid any out-diffusion of copper into the surrounding dielectric material, as copper may readily migrate to sensitive semiconductor areas, thereby significantly changing the characteristics thereof. On the other hand, the barrier material may suppress the diffusion of reactive components into the metal region. The barrier material provided between the copper and the dielectric material should exhibit, however, in addition to the required barrier characteristics, good adhesion to the dielectric material as well as to the copper and should also have as low an electrical resistance as possible so as to not unduly compromise the electrical properties of the interconnect structure. It turns out, however, that a single material may not readily meet the requirements imposed on a desired barrier material. Hence, a mixture of materials may be frequently used to provide the desired barrier characteristics. For instance, a bi-layer comprised of tantalum and tantalum nitride is often used as a barrier material in combination with a copper damascene metallization layer. Tantalum, which effectively blocks copper atoms from diffusing into an adjacent material even when provided in extremely thin layers, however, exhibits only a poor adhesion to a plurality of dielectric materials, such as silicon dioxide based dielectrics, so that a copper interconnection including a tantalum barrier layer may suffer from reduced mechanical stability especially during the chemical mechanical polishing of the metallization layer, which is required for removing excess copper and planarizing the surface for the provision of a further metallization layer. The reduced mechanical stability during the CMP process may, however, entail several reliability concerns in view of reduced thermal and electrical conductivity of the interconnections. On the other hand, tantalum nitride exhibits excellent adhesion to silicon dioxide based dielectrics, but has very poor adhesion to copper. Consequently, in advanced integrated circuits having a copper-based metallization, typically a barrier bi-layer of tantalum nitride/tantalum is used.
Due to the demand for a low resistance of the interconnect structure in combination with the continuous reduction of the dimensions of the circuit elements and associated therewith of the metal lines and vias, the thickness of the barrier layer has to be reduced, while nevertheless providing the required barrier effect. It has been recognized that tantalum nitride provides excellent barrier characteristics even if applied with a thickness of only a few nanometers and even less. Thus, sophisticated deposition techniques have been developed for forming thin tantalum nitride layers with high conformality even in high aspect ratio openings, such as the vias of advanced metallization structures. Corresponding deposition techniques have a substantially self-limiting deposition behavior and thus allow extremely thin layers to be deposited with a reliable coverage even at critical locations, such as the sidewall areas of vias and the like. Hence, respective self-limiting techniques, also referred to as atomic layer deposition (ALD), have been used for forming barrier layers of copper-based interconnect structures. Although these techniques represent a promising approach for further device scaling, there is still room for further improvements, as will be described in more detail with reference to FIGS. 1a-1c. 
In FIG. 1a, a metallization structure 100 comprises a substrate 101, for example, a semiconductor substrate, bearing a plurality of individual circuit elements (not shown), such as transistors, resistors, capacitors and the like. The substrate 101 is to represent any type of appropriate substrate with or without any additional circuit elements and may, in particular, represent sophisticated integrated circuit substrates having included therein circuit elements with critical feature sizes in the deep submicron regime. A first dielectric layer 102 is formed above the substrate 101 and includes a metal region 104 comprised of a metal line 103, such as a copper line, a first barrier layer 106 comprised of tantalum, and a second barrier layer 105 comprised of tantalum nitride. The dielectric layer 102, which may include an etch stop layer, in combination with the metal interconnection 104, may represent a first metallization layer. A second dielectric layer 107 comprised of silicon dioxide or a silicon dioxide based dielectric material or any other appropriate dielectric material is formed above the first dielectric layer 102 and has formed therein a trench 109 and a via 108 connecting to the metal line 103. A pre-form 110A of first barrier layer 110 is formed on exposed surface areas such as the inner surfaces of the via 108 and the trench 109.
A typical process flow for forming the metallization structure 100 as shown in FIG. 1a may include the following steps, wherein, for the sake of simplicity, only the formation of the second metallization layer, i.e., of the second dielectric layer 107 and the metal interconnection to be formed therein, will be described in detail as the processes in forming the metal interconnection 104 in the first dielectric layer 102 may substantially involve the same process steps. Thus, after planarizing the dielectric layer 102, including the metal interconnection 104, the etch stop layer may be deposited, followed by the deposition of the dielectric layer 107 by well-known deposition methods, such as plasma enhanced chemical vapor deposition (PECVD). Subsequently, the dielectric layer 107 is patterned by well-known photolithography and anisotropic etch techniques, wherein optionally an intermediate etch stop layer (not shown) may be used in patterning the trench 109. It should further be noted that different approaches may be employed in forming the trench 109 and the via 108, such as a so-called via first trench last approach, or a trench first via last approach, wherein, in the former approach, the via 108 may be filled with metal prior to the formation of the trench 109. In the present example, a so-called dual damascene technique is described in which the trench 109 and the via 108 are simultaneously filled with metal. After forming the via 108 and the trench 109, the pre-form 110A of the first barrier layer 110 is deposited by a self-limiting deposition process 111, in which, in a first step, appropriate gases are applied that may be obtained from, for instance, metal organic compounds, such as pentakis (dimethylamino) Ta (PDMAT). In other cases, the layer 110A may be formed on the basis of tantalum chloride, if the presence of chlorine may not negatively affect the reliability of the resulting interconnect structure. Generally, the deposition of the thin barrier layer 110, typically with a thickness in the range of approximately 1-15 nm or even less, in a reliable manner on the entire inner surfaces of the trench 109 and the via 108, wherein, in particular, the via 108 may have a large aspect ratio, may be accomplished on the basis of the ALD process 111. Generally, it is desirable to obtain a reliable coverage of the sidewalls of the trench 109 and the via 108 with a minimum thickness of the layer 110 so that only a minimum amount of space is “consumed” by the layer 110. Increasing the thickness of the barrier layer 110 would otherwise unduly compromise the electrical conductivity of the interconnection to be formed in the via 108 and the trench 109, especially when the feature sizes in the metallization level are scaled to 0.2 μm and less.
FIG. 1b schematically shows the metallization structure 100 during a second step of the ALD process 111, wherein a second gaseous ambient is established to form the tantalum nitride layer 110. For instance, activated nitrogen may be introduced to initiate the desired surface reaction on the basis of the pre-form 110A, wherein the reaction and thus the final layer thickness is determined by the pre-form 110A. Thus, a continuous coverage of the inner surfaces of the trench 109 and the via 108 is obtained in order to provide a reliable diffusion barrier, in particular at critical locations, such as the sidewalls of the via 108 and the trench 109. However, tantalum nitride exhibits a moderately high electrical resistance, which may result in an undue overall resistance of the via 108 after providing the tantalum material and filling the structure with a copper-based material. Therefore, prior to forming a second barrier layer on the basis of tantalum, the layer 110 is removed at the via bottom 108B. To this end, a sputter etch process is typically performed with a high degree of directionality.
FIG. 1c schematically illustrates the metallization structure 100 during a corresponding sputter etch process 112 for opening the via bottom 108B. During the process 112, a corresponding material removal may also occur in other substantially horizontal portions, for instance in the trench 109, thereby also significantly affecting the highly sensitive low-k dielectric material 107. Moreover, during the aggressive re-sputtering 112 at the via bottom 108B, copper atoms may also be liberated into the etch ambient, which may deposit at undesired locations, thereby possibly resulting, in combination with the damaged low-k dielectric, in a reduced performance and possibly in a lower reliability of the finally obtained interconnect structure.
After the sputter etch process 112, tantalum may be deposited, for instance by sputter deposition, in order to provide the desired barrier and adhesion characteristics, as previously explained.
FIG. 1d schematically illustrates the metallization structure 100 with a second barrier layer 113 comprised of tantalum, wherein the layer 113 may extend into the metal line 103 due to the preceding sputter etch process 112. Similarly, the trench 109 may exhibit damaged areas which may result in respective line irregularities.
Consequently, although the ALD process of the tantalum nitride layer 110 may provide high reliability with respect to coverage of the critical via and trench sidewalls, the subsequent aggressive removal of the high resistance tantalum nitride material may cause damage in other sensitive device areas, thereby reducing performance and reliability of the interconnect structure, in particular when highly scaled semiconductor devices are considered.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.